Generally, circuit devices for protection against an ESD event are utilized in many electronic circuit designs to discharge high voltages and high currents due to the ESD event at a device and to prevent damage to other internal circuitry of the device.
FIG. 1A schematically illustrates a traditional silicon-controlled rectifier (SCR) 100 circuitry utilized in an ESD protection circuit design, and graph 150 in FIG. 1B depicts a transmission-line-pulse (TLP) test result showing a current (e.g., ampere, I) vs. voltage (I-V) curve characterizing the ESD performance associated with the SCR circuit 100. Usually, the SCR 100 ESD circuitry can provide a high ESD protection performance while requiring a small layout area in an integrated-circuit (IC) design. However, as indicated in the graph 150, the SCR 100 circuitry requires a high trigger voltage (Vt1) 151 before it can be enabled to provide an adequate ESD protection to other circuits in a device and prevent any damages due to an ESD event. Moreover, as indicated in the graph 150, levels of a trigger current (It1) 153, a holding current (Ih) 155, and a holding voltage (Vh) 157 are low, which can cause performance issues such as latch-up (e.g., a parasitic low impedance path between a power supply's power rails, which can stay on and conduct large amounts of current) in different areas of circuitry affected by an ESD event.
FIG. 2 schematically illustrates another ESD circuit 200, which includes utilization of metal-oxide-semiconductor field-effect transistors (MOSFETs). In this example, the ESD circuit 200 is an NMOS (n-type MOSFET) based resistor-capacitor (RC) clamp including resistor 205 (R), capacitor 207 (C), NMOS transistor 203, NMOS transistors 209 and PMOS transistors 211. Further, with selection of proper values for R and C, a suitable RC time constant (e.g., R×C=time required to electrically charge the capacitor, via the resistor, to a certain percentage of the capacitor's full capacity) can provide for a lower trigger voltage (e.g., Vt1) and a quicker turn-on time so that the circuit 200 can quickly turn on and effectively protect other circuits in a device from being destroyed by an ESD event. Additionally, the RC-clamp provides for a lower latch-up risk wherein any possible latch-up current may easily be discharged while preventing formation of other latch-up paths. However, the NMOS based RC-clamp in the circuit 200 would require a very large layout area (e.g., a large NMOS 203) in order to discharge an ESD current and would not be efficient (e.g., cost effective) for implementation in an integrated circuit design in order to provide an ESD protection level as high as the SCR circuit 100.
A need therefore exists for a well performing and cost effective ESD solution and enabling methodology.